1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular to a semiconductor storage device having a configuration and operation which can screen signal voltage distribution of stored data.
2. Description of the Related Art
With the prevalence of portable devices, nonvolatile memories have recently been used frequently in which memory contents are not erased even if the power is turned off. One of these nonvolatile memories is a ferroelectric memory (FeRAM) which stores data in ferroelectric capacitors, along with a flash memory, an SRAM and the like.
The ferroelectric memory is known to include a so-called 1T1C type which serially connects a memory transistor (T) and a ferroelectric capacitor (C) to configure a memory cell, and a 2T2C type in which the memory cells are complementarily arranged. Such a FeRAM has problems that an element area cannot be below 8F2 (F is the minimum line width in a design rule) in the case of a folded bit line scheme and that the operation speed is lower than a DRAM because plate lines with large capacitance are driven.
In order to solve these problems, a (chain-type) ferroelectric memory having a series connection of TC parallel-connection units has also been devised in which the memory transistor and the ferroelectric capacitor are connected in parallel and units thereof are serially connected in a chain form, and its configuration and operation are described in detail, for example, in Jpn. Pat. Appln. KOKAI Publication No. 2000-339973 by the present inventors. It is to be noted that this Published Japanese Patent discloses a novel configuration which can reduce the storage polarization amount of the memory cells and occurrence of disturbance.
The ferroelectric memory is a memory utilizing hysteresis characteristics of ferroelectrics in which polarization caused when an electric field is applied remains even when the electric field is not applied and in which the direction of polarization is reversed when an electric field opposite to the above electric field is applied. While “1”, “0” are stored in the direction of the polarization, whether predetermined data “1”, “0” can be written or read in each memory cell is tested during manufacture of the ferroelectric memory, thereby judging if a product is good or not. In conventional methods, even if a memory cell is judged to be a good product, it is unclear what operation margin the memory cell has.
To solve the above-described problems, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-216498 quantitatively measures a bit line voltage due to remnant polarization of the ferro-electric capacitor of the ferro-electric memory to enable evaluation of characteristic displacement of the ferroelectric capacitor and the degree of deterioration.
As described above, the ferroelectric memory stores “0”, “1” in the direction of polarization of the ferroelectric, but “0”, “1” are formed with distributions in one chip due to irregular manufacturing conditions involved with positional problems in the chip. Thus, those products in which “0” adjoins “1” and the operation margin is thus not sufficient pass the test, and this might cause reliability problems later on.
It has therefore been desired to realize a semiconductor storage device which can screen those with a narrow operation margin in signal voltage distribution of binary data.